So… Some people here at Toppoint got themselves a Papilio Pro LX9 FPGA development board, containing an Xilinx Spartan XC6SLX9 FPGA with 64 MBit SPI Flash, 64 MBit SDRAM and 48 I/O pins. This article is about how I got my first design running on it.

Among the downloadable software for this board is the Papilio Loader 2.6, written in Java. The included build and run scripts did not work “out of the box”. The commands that did work to build it are:

javac -sourcepath src -d bin src/net/gadgetfactory/papilio/loader/PapilioLoader.java
jar cfm0 papilio-loader.jar PapilioLoader.mf -C bin .

To run:

java -jar papilio-loader.jar

Also, I needed to install libftdi:i386 on my amd64 system to get it working.

I won’t cover acquiring and installing Xilinx ISE DS. I already had that installed (version 13.4), and whipping up a quick design for this board wasn’t too hard.

blinky.vhd:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity blinky is
    Port (
        CLK : in STD_LOGIC;
        LED1 : out STD_LOGIC);
end blinky;

architecture Behavioral of blinky is

    constant widthwidth : natural := 5;
    constant width : natural := 2 ** widthwidth;
    signal counter : unsigned(width-1 downto 0) := (others => '0');
    signal p : natural range 0 to width-1 := 0;
    signal l : std_logic := '0';

begin

    process (CLK)
    begin
        if rising_edge(CLK) then
            if (counter = 0) then
                counter(p) <= '1';
                if (l = '0') then
                    l <= '1';
                else
                    l <= '0';
                    p <= p + 1;
                end if;
            else
                counter <= counter - 1;
                LED1 <= l;
            end if;
        end if;
    end process;

end Behavioral;

blinky.ucf:

## Prohibit the automatic placement of pins that are connected to VCC or GND for configuration.
CONFIG PROHIBIT=P144;
CONFIG PROHIBIT=P69;
CONFIG PROHIBIT=P60;

NET CLK            LOC="P94"  | IOSTANDARD=LVTTL | PERIOD=31.25ns;               # CLK
NET LED1           LOC="P112" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=SLOW;          # LED1

The LED1 will blink fast and get slower, every cycle taking double the time as before. When p overflows, it starts from the beginning.